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Essay / Research Paper Abstract
A 12 page paper discussing Ubicom's SX family of controllers, focusing on ports and bus interface. Memory chips have continued to evolve over the years since the earliest semiconductor. Increasingly, they are smaller in size but have consistently-increasing storage and retrieval capabilities. One type, the Ubicom SX series, is described here. Bibliography lists 6 sources.
Page Count:
12 pages (~225 words per page)
File: CC6_KSmemChips.rtf
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Unformatted sample text from the term paper:
continued to evolve over the years since the earliest semiconductor. Increasingly, they are smaller in size but have consistently-increasing storage and retrieval capabilities. One type, the Ubicom SX
series, is described here. Overview Ubicoms SX line of configurable communications controllers are manufactured using
an advanced CMOS process technology that includes a RISC-based architecture. The result is a product that provides high-speed computation, flexible I/O control, and efficient data manipulation (Configurable Communications Controllers,
2000). The chip operates most effectively at 50/75 MHz and on a set of single-cycle instructions. The architecture of the entire SX
family is deterministic and reprogramable. Ubicom says that this combination of features is unique within the industry and "enables the device to implement hard real-time functions as software modules
(Virtual PeripheralTM) to replace traditional hardware functions. On-chip functions include a general-purpose 8-bit timer with prescaler, an analog comparator, a brown-out detector, a watchdog timer, a power-save mode with
multisource wakeup capability, an internal R/C oscillator, user-selectable clock modes, and high-current outputs" (Configurable Communications Controllers, 2000). Features
The SX family includes six chips, all of which yield 50 MIPS performance. SX18AC/SX20AC/SX28AC have 50 MHz operation with a 20 ns instruction cycle and a
60 ns internal interrupt response. SX18AC75/SX20AC75/SX28AC75 operate at 75 MHz with a 13.3 ns instruction cycle and 39.9 ns internal interrupt response.
All have EE/FLASH Program Memory and SRAM Data Memory with access time of less than 10 ns in single cycle access. EE/Flash is rated for more than 10,000 rewrite
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